1. Field of the Invention
The present invention relates to a differential amplifier and, particularly, to a differential amplifier used in a source driver of a liquid crystal display panel.
2. Description of Related Art
An active matrix liquid crystal display device is known that includes a thin film transistor liquid crystal display (TFT-LCD), which is a TFT type liquid crystal display panel, a source driver placed on the upper side of the TFT-LCD and a gate driver placed on the side surface of the TFT-LCD. In such a liquid crystal display device, a differential amplifier for driving a capacitor load of a pixel is used in the source driver.
In the TFT-LCD, AC driving is performed in order to prevent burn-in due to DC voltage application. The AC driving of the LCD is a driving method that inverts the writing polarity centered at a common level every frame or line, and there are a plurality of types such as “frame inversion”, “gate line inversion”, “drain line inversion” and “dot inversion”. The “frame inversion” is a method in which the writing polarity is inverted every frame, and the “gate line inversion” is a method in which the writing polarity in the scan line direction is the same and the polarity is inverted every N (N is an integer of two or above) lines in each frame and further the writing polarity is inverted every frame. The “drain line inversion” is a method in which the writing polarity in the data line direction is the same in each frame and the writing polarity is inverted every frame. The “dot inversion” is a method in which the writing polarity of adjacent pixels is inverted in each frame and further the writing polarity is inverted every frame.
FIG. 8 shows a source driver 10 and a TFT-LCD (which is also referred to hereinafter simply as an LCD) 20 in a liquid crystal display device. The source driver 10 includes a data register 11 that captures digital display signals R, G and B of a given number of bits (e.g. eight bits), a latch circuit 12 that latches the digital display signal in synchronization with a strobe signal ST, a D/A converter 13 that is composed of digital-to-analog converters of N (N is an integer of two or above) stages in parallel, a liquid crystal grayscale voltage generator 14 that has gamma conversion characteristics conforming to the characteristics of liquid crystals, and an N-number of voltage followers 15 (a voltage follower 15_1 to a voltage follower 15_N) that buffer the voltage from the D/A converter 13.
The LCD 20 includes TFTs 16 (a TFT 16_1 to a TFT 16_N) and pixel capacitors 17 (a pixel capacitor 17_1 to a pixel capacitor 17_N). Each TFT 16 is placed at the intersection between a data line and a scan line. The gate of each TFT 16 is connected to the scan line, and the source is connected to the data line. One end of each pixel capacitor 17 is connected to the drain of the TFT 16, and the other end is connected to a COM terminal. Although FIG. 8 shows the configuration of the LCD 20 of only one line for convenience of description, an actual LCD includes M (M is an integer of two or above) lines of the TFTs 16 shown in FIG. 8.
During the operation of the liquid crystal display device, a gate driver, which is not shown, sequentially drives the gates of the TFTs in each line.
The D/A converter 13 converts the digital display signal from the latch circuit 12 from digital to analog and supplies the obtained voltage to each of the N-number of the voltage follower 15_1 to the voltage follower 15_N. The voltage follower 15_1 to the voltage follower 15_N are differential amplifiers, and they perform differential amplification of the voltage supplied from the D/A converter 13 and apply the result to the pixel capacitor 17_1 to the pixel capacitor 17_N through the TFT 16_1 to the TFT 16_N.
The liquid crystal grayscale voltage generator 14 generates a reference voltage and supplies it to the D/A converter 13. The D/A converter 13 selects the reference voltage by a decoder composed of a ROM switch or the like, which is not shown.
The liquid crystal grayscale voltage generator 14 includes a resistance ladder circuit, for example, and it is driven by the voltage followers so as to reduce the impedance at each reference voltage point or to adjust the reference voltage.
Generally, writing to pixels of an LCD is performed by a differential amplifier (which is the voltage follower 15 in the example of FIG. 8) that serves as an output circuit of a source driver of the LCD. FIG. 9 is an equivalent of FIG. 10 of Japanese Patent No. 3550016, and it shows the differential amplifier disclosed in Japanese Patent No. 3550016. In the following description, a P-channel MOS transistor and an N-channel MOS transistor are referred to simply as a P-transistor and an N-transistor, respectively.
The differential amplifier shown in FIG. 9 is a high voltage differential amplifier for driving a grayscale voltage that is equal to or higher than one-half of a power supply voltage. In this differential amplifier, a differential stage includes an N-transistor differential pair (NM61 and NM62) to which a voltage that is equal to or higher than one-half of the voltage of a power supply 2, which is a higher voltage power supply, and equal to or lower than the voltage of the power supply 2 can be input. In the case of inputting a voltage that is equal to or higher than the voltage of a power supply 1, which is a lower voltage power supply, and equal to or lower than one-half of the voltage of the power supply 2, a differential amplifier including a P-transistor differential pair may be used.
As shown in FIG. 9, the sources of the NM61 and the NM62 are connected to each other, and the gate of the NM61 is connected to a − input terminal, and the gate of the NM62 is connected to a + input terminal. Further, an N-transistor NM63 is connected between the N-transistor differential pair and the power supply 1. The NM63 functions as a constant current source of the input stage, having the source connected to the power supply 1, the drain connected to the sources of the NM61 and the NM62, and the gate connected to a constant voltage source terminal bias 3.
The sources of P-transistors PM53 and PM54 are connected to the power supply 2. The gate and the drain of the PM53 and the gate of the PM54 are connected to the drain of the NM61, and the drain of the PM54 is connected to the drain of the NM62.
The source of a P-transistor PM55 is connected to the power supply 2 and the gate is connected to the drains of the PM54 and the NM62. Further, an N-transistor NM64 is connected between the drain of the PM55 and the power supply 1. The NM64 functions as a constant current source of the output stage, having the source connected to the power supply 1, the drain connected to the drain of the PM55, and the gate connected to the constant voltage source terminal bias 3.
The drain of the PM55 is connected to one end of a phase compensation capacitor C. A P-transistor PM56 having the gate connected to a constant voltage source terminal bias 4 and the source connected to the drain of the PM54 is connected between the other end of the phase compensation capacitor C and the gate of the PM55, thus serving as a zero point resistor.
The operation when the differential amplifier shown in FIG. 9 is connected in a voltage follower configuration is described hereinafter. The voltage follower connection is connecting the − input terminal and the output terminal of the differential amplifier. The differential amplifier in the voltage follower configuration is an amplifier with a high input impedance and a low output impedance, which outputs a voltage that is input to the + input terminal to the output terminal as it is.
If the voltages at the + input terminal and the output terminal are equal, a current that is one-half of the drain current flowing through the N-transistor NM63 in the input stage flows into the drains of the NM61 and the NM62.
If the voltage at the + input terminal becomes higher than the voltage at the output terminal, the drain current flowing through the N-transistor NM63 in the input stage flows into the NM62, and the current flowing into the NM61 becomes zero. Accordingly, the current flowing into the PM53 and the PM54 also becomes zero. In this case, the phase compensation capacitor C is discharged by a difference between the current of the PM54 and the current of the NM62, the gate voltage of the PM55 decreases, an output load capacitor is charged by the current of the PM55, and the voltage at the output terminal becomes higher according to the voltage at the + input terminal, so that the differential amplifier outputs a rising edge.
If the voltage at the + input terminal becomes lower than the voltage at the output terminal, the current flowing into the NM62 becomes zero, and the drain current flowing through the N-transistor NM63 in the input stage flows into the NM61. Accordingly, the drain current flowing through the N-transistor NM63 in the input stage flows also into the PM53 and the PM54. In this case, the phase compensation capacitor C is charged by a difference between the current of the PM54 and the current of the NM62, the gate voltage of the PM55 increases, the output load capacitor is discharged by the current of the N-transistor NM64 in the output stage, and the voltage at the output terminal becomes lower according to the voltage at the + input terminal, so that the differential amplifier outputs a falling edge.
In this manner, the voltage at the output terminal changes responsive to a change in the voltage at the + input terminal, the rising speed is determined by the current capacity of the constant current source NM63 in the input stage, the phase compensation capacitor C and the PM55, and the falling speed is determined by the current capacity of the constant current source NM63 in the input stage, the phase compensation capacitor C and the constant current source NM64 in the output stage.
FIG. 10 shows another example of a differential amplifier. The differential amplifier shown in FIG. 10 is also a high voltage differential amplifier for driving a grayscale voltage that is equal to or higher than one-half of a power supply voltage. In this differential amplifier, the input stage includes an N-transistor differential pair (MN1 and MN2) to which a voltage that is equal to or higher than one-half of the voltage of a VDD, which is a higher voltage power supply, and equal to or lower than the voltage of the VDD can be input. In the case of inputting a voltage that is equal to or higher than the voltage of a VSS, which is a lower voltage power supply, and equal to or lower than one-half of the voltage of the VDD, a differential amplifier including a P-transistor differential pair may be used. In the following description and drawings, “+ input terminal” is denoted by “INP” and “− input terminal” is denoted by “INM”.
As shown in FIG. 10, the sources of the MN1 and the MN2 located in the input stage are connected to each other, and the gate of the MN1 is connected to the input terminal INM, and the gate of the MN2 is connected to the input terminal INP. An N-transistor MN10 is connected between the N-transistor differential pair and the VSS. The MN10 functions as a constant current source of the input stage, having the source connected to the VSS, the drain connected to the sources of the MN1 and the MN2, and the gate connected to a constant voltage source terminal BN1.
The sources of P-transistors MP3 and MP4 located in the intermediate stage are connected to the VDD. The gate and the drain of the MP3 and the gate of the MP4 are connected to the drain of the MN1, and the drain of the MP4 is connected to the drain of the MN2.
The source of a P-transistor MP7 is connected to the VDD, the gate is connected to a constant voltage source terminal BP3, and the drain is connected to the drains of the MP4 and the MN2. The source of a P-transistor MP8 is connected to the drain of the MP7, the gate is connected to a constant voltage source terminal BP4, and the drain is connected to the drain of an N-transistor MN7. The source of an N-transistor MN8 is connected to the drain of the MN7, the gate is connected to a constant voltage source terminal BN4, and the drain is connected to the drain of the MP7.
The source of a P-transistor MP9 located in the output stage is connected to the VDD, and the gate is connected to the drain of the MP7. The source of an N-transistor MN9 is connected to the VSS, and the gate is connected to the drain of the MN7. The drains of the MP9 and the MN9 are connected to each other, serving as an output terminal OUT.
Further, one end of a phase compensation capacitor C1 is connected to the drain of the MP9. The other end of the phase compensation capacitor C1 is connected to the drain of the MP7 and the gate of the MP9.
The operation when the differential amplifier shown in FIG. 10 is connected in a voltage follower configuration is described hereinafter.
If the voltages at the input terminal INP and the output terminal OUT are equal, a current that is one-half of the drain current flowing through the N-transistor MN10 in the input stage flows both into the MN1 and the MN2.
If the voltage at the input terminal INP becomes higher than the voltage at the output terminal OUT, the drain current flowing through the MN10 flows into the MN2, and the current flowing into the MN1 becomes zero. Accordingly, the current flowing into the MP3 and the MP4 also becomes zero. In this case, the phase compensation capacitor C1 is discharged by a difference between the current of the MP4 and the current of the MN2, the gate voltage of the MP9 decreases, an output load capacitor is charged by the current of the MP9, and the voltage at the output terminal OUT becomes higher according to the voltage at the input terminal INP.
If the voltage at the input terminal INP becomes lower than the voltage at the output terminal OUT, the current flowing into the MN2 becomes zero, and the drain current flowing through the MN10 flows into the MN1. Accordingly, the drain current flowing through the MN10 flows also into the MP3 and the MP4. In this case, the phase compensation capacitor C is charged by a difference between the current of the MP4 and the current of the MN2, and the gate voltage of the MP9 increases. Because the gate-to-source voltage (VGS) of the MP8 becomes larger with an increase in the gate voltage of the MP9, the drain current of the MP7 flows into the MP8 more than into the MN8. The current flowing into the MN8 thereby decreases, and the VGS of the MN8 becomes smaller, and the gate voltage of the MN9 increases. Then, the output load capacitor is discharged by the current of the MN9, and the voltage at the output terminal OUT becomes lower according to the voltage at the input terminal INP.
In this manner, the voltage at the output terminal OUT changes responsive to a change in the voltage at the input terminal INP, the rising speed is determined by the current capacity of the constant current source MN10 in the input stage, the phase compensation capacitor C1 and the MP9, and the falling speed is determined by the current capacity of the constant current source MN10 in the input stage, the phase compensation capacitor C1 and the MN9.